As it is well known in the specific field of the manufacturing of semiconductor integrated memory devices, at present the market for nonvolatile memories typically requires higher and higher access speeds against lower and lower supply voltages. This need results from the desire of reducing the power consumption as much as possible and increasing, in the meantime, the so-called throughput.
Within this field the output buffer stages play a fundamental role. Their switching speed is strictly connected to the memory access time and the several switchings they are subjected to strongly affect the power consumption. For example, to optimize the power consumption in an output stage realized according to CMOS technology, the periods of time when the PMOS and NMOS transistors are simultaneously in the saturation zone may have to be reduced to the minimum. In fact, during the transitions between one logic level and another, there is typically a period when both the MOS transistors are in the saturation zone and generate a current between the power supply and ground, called the OVERLAP current.
By way of example, we now consider the case of a CMOS output stage which should drive a capacitive load Cload, as shown in FIG. 1. In this case it may be important to ensure that the charging occurs through the PMOS transistor with the other NMOS transistor in the cut-off state. Instead, the discharging step should occur through the NMOS transistor when the other PMOS transistor is cut-off. In this way during the charging and discharging steps of the capacitor Cload, there may never be an OVERLAP current.
However, to ensure that these conditions occur, the two control signals applied to the respective gate terminals of the NMOS and PMOS transistors should be split, as shown in FIG. 2. When the output has to pass from the high logic value to the low one, which corresponds to the discharging step of the capacitor, first the PMOS transistor should be cut-off and then the NMOS transistor should go into conduction. Instead, in the other transition, it's the NMOS transistor that should be cut-off before the PMOS transistor goes into conduction. The timing of the just described events is shown in FIG. 4.
From what has been said, it can be inferred that the generation of the two control signals is anything but simple, and it directly affects the buffer performance. It should be also highlighted that the rise speed of the two control signals and their pattern are directly connected to the disturbance induced on the power supply by the buffer switchings. To avoid too high noise peaks, the turn-on of the PMOS transistor and of the NMOS transistor is controlled so that the charge/discharge current of the capacitor Cload has a constant slope (dI/dt=const).
The noise induced on the power supply Vdd is substantially caused by the voltage variation across the parasitic inductor/resistor group, inevitably in the supply line. To better understand the phenomena previously described, reference can be made to FIG. 3 that shows a schematic block diagram comprising an output buffer and the main circuit blocks operating therewith.
FIGS. 5 and 6 respectively show in detail: the supply block, and an example of circuit for the generation of the driving controls of the buffer stage. The most commonly used approach for the generation of the control signals GATEP and GATEN is shown in the example of FIG. 6. This circuit ensures a constant dI/dt during the first charging and discharging steps of the capacitor Cload.
The limitation of sudden current variations on the capacitor results in the lack of spikes on the supply voltage. The variations of inductive nature on the power supply are proportional to the variation of the current absorbed by the supply source LdI/dt, whereas the variations of a resistive nature are proportional to the current required by the source.
What has been so far described allows generating a control signal with a constant slope. In the period of time elapsing between the start of the control signal and the overtaking of the threshold voltage of the MOS transistors of the output driver, it is possible to speed up the times, since the load driving step is still to come. A control is then attained, so called with two slopes, the first steeper between the instant zero and the overtaking of the threshold voltage of the MOS transistor (i.e. the PMOS transistor during the charging and the NMOS transistor during the discharging) and a second slope, less steep, until the output switchings are reached.
FIGS. 7 and 8 show the two control signals GATEN and GATEP and the respective circuit schematic diagrams for the generation of these control signals with two slopes. The first section, with the steeper slope, is obtained by a resistor R1, whereas the second, with a less steep slope, is obtained with the introduction of a resistor R2 and by switching of a signal CONTROL_1N or CONTROL_1P, according to the transistor being driven.
This approach however, has a drawback due to the fact that the resistors used for obtaining the two different slopes make sure that the voltage values on the gate terminals of the transistors of the buffer stage do not go to zero (in the case of the NMOS) or to Vdd (in the case of the PMOS) also when the variation has occurred. To address this problem the known technique proposes the scheme of FIGS. 9 and 10 that realize a control with three slopes.
With respect to the previous approach the presence can be appreciated of a MOS transistor which completely short-circuits the resistor once the transition has occurred. It is in fact to be remembered that after an initial period when the current across the capacitor would tend to vary in a sudden way, causing noise on the power supply, the current tends to zero in an exponential way, therefore the control is not necessary any more. The scheme of FIGS. 9 and 10 differs from that of FIGS. 7 and 8 with the introduction of the signals CONTROL_2N and CONTROL_2P. Such signals, obtained through a suitable delay by the signal CONTROL_1N or CONTROL_1P, allow driving the NMOS transistor that short-circuits both the resistor R1 and the resistor R2. The above delay is preferably obtained by a chain of inverters in cascade, being suitably sized and as seen in the figures.
Although advantageous under several aspects, this approach also exhibits a limitation. In the applications to multi-level memories there is the need of obtaining low output impedances from the buffers and the use of the latter approach described has revealed itself to be a problem since low output impedances result in the need of using resistors of too low a value that cannot be practically realized or which are too subject to variations due to the manufacturing process. Therefore the approach of generating control signals with the linear profile at intervals obtained by resistors has revealed itself to be difficult to be applied.
The problem addressed by the present invention is that of providing a driving circuit for an output buffer stage incorporated in a memory electronic device, having such structural and functional characteristics as to allow the generation of driving signals with a linear pattern at intervals, the signal being however generated by components of the MOS or CMOS type, thus overcoming the limits of the approaches proposed by the prior art.